Some processors, such as microprocessors, use one or more levels of cache memory in a memory hierarchy to reduce access time to data, and thus to improve performance. Some processors have sleep and/or low-power modes wherein much of the logic of the processor is powered-off and does not retain state, saving overall system power when the processor is not in use. Power savings of a sleep mode, however, is mitigated due to issues with one or more levels of cache associated with the processor. Keeping the caches powered on during sleep mode allows them to retain state, but consumes significant amounts of power, leading to increased cooling costs, reduced battery life, and reduced reliability. Powering off the caches in sleep mode consumes power in a different manner, due to reloading state into the caches from demand misses in empty (after being powered off) caches. In some processors, demand misses consume power and/or reduce performance by causing the processor to be powered on, but to be idle until the demand miss is satisfied.
Some processors and/or processor systems provide one or more caches and one or more buffers, leading, in some usage scenarios, to one or more of increased die size, increased power consumption, or complexity. Examples of the buffers include Input/Output (I/O) buffers (such as for use with a direct memory access controller) and graphics buffers.